Cost control, production efficiency, cycle time and yield are critical quality benchmark for nanoelectronics productions.-
An increasingly important downside of nano-CMOS technology scaling is the
fact that the scaling of feature sizes cannot be accompanied by a suitable scaling of geometric tolerances.
In addition, when getting into deep miniaturized dimensions, phenomena like edges or surfaces roughness, or the fluctuation of the number of doping atoms within the channels are becoming increasingly significant.
As a result, the figures of merit of a circuit, such as performance and power, have become extremely sensitive to uncontrollable statistical process variations (PV).
To ensure stable manufacturability and secure high manufacturing yield, it is mandatory to manage complete design flows and to link traditional methods for design with Technology CAD models.
In this context, multi-objective optimization algorithms and statistical analysis are essential on device and behavioral levels to secure high yielding by modeling the impact of inevitable process variations and doping fluctuations on IC performance.
Statistical circuit modeling is a viable solution to nano-electronics production quality, on which the European Union is already investing.
The project intends to create a partnership between academies, industry and SME so to create a Transfer of Knowledge between the organizations in order to pass the mathematical know how on multi-objective optimization, symbolic techniques and numerical statistical simulation on one side, the industrial design experience, real test cases availability and Electronic Design Automation (EDA) software modeling skills on the other.
The scope of the research activity will be to create PV-aware and PV-robust circuit design techniques, tools and models in the frame of the analogue and mixed-signal circuit industrial design.